There have been developed memory circuits including a magnetoresistive element as a memory cell. Such a memory circuit compares the potential of a bit line varying according to data stored in a memory cell with a reference voltage to determine and output the stored data.
In a memory circuit disclosed in Patent Literature 1, a reference resistor Rref is used in order to generate a reference voltage. The reference resistor Rref includes a configuration with series connection of a circuit with parallel connection of two magnetoresistive elements in a parallel state and a circuit with parallel connection of two magnetoresistive elements in an antiparallel state. The parallel state means a state in which the magnetization directions of the pinned layers and free layers of the magnetoresistive elements are the same as each other, while the antiparallel state means a state in which the magnetization directions of the pinned layers and free layers of the magnetoresistive elements are opposite to each other.
In the reference resistor Rfef, (Rp+Rap)/2 is satisfied, in which Rp is a resistance value in a case in which the magnetoresistive elements are in the parallel state, and Rap is a resistance value in a case in which the magnetoresistive elements are in the antiparallel state.
In addition, the memory circuit disclosed in Patent Literature 1 includes a resistor for adjustment. The resistor for adjustment is connected to the reference resistor Rref and has a resistance value half the resistance value of a bit line.
A memory circuit disclosed in Patent Literature 2 includes a configuration in which a reference cell is arranged in each row of a memory cell array. The memory circuit selects a reference cell in the same row as that of a memory cell to be accessed. The resistance value of each reference cell is set to an intermediate level between the resistance values Rmax and Rmin of a corresponding memory cell. In addition, Patent Literature 2 discloses, as a technique of setting the resistance value of a reference cell to such a value, a technique of writing stored data corresponding to a resistance value Rmin into a reference cell to adjust the size and gate voltage of a transistor for selection.